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1. product profile 1.1 general description the blm7g1822s-40ab(g) is a dual secti on, asymmetric, 2-stage power mmic using nxp?s state of the art gen7 ldmos technology. this multiband device is perfectly suited as small cell final in doherty configuration, or as general purpose driver in the 1805 mhz to 2170 mhz frequency range. available in gull wing or straight lead outline. 1.2 features and benefits ? designed for broadband operation (frequency 1805 mhz to 2170 mhz) ? high section-to-section isolatio n enabling multip le combinations ? high doherty efficiency thanks to 2 : 1 asymmetry ? integrated temperature compensated bias ? biasing of individual stages is externally accessible ? integrated esd protection ? excellent thermal stability ? high power gain ? on-chip matching for ease of use ? compliant to directive 2002/ 95/ec, regarding restricti on of hazardous substances (rohs) 1.3 applications ? rf power mmic for w-cdma base stations in the 1805 mhz to 2170 mhz frequency range. possible circuit topologies are the following as also depicted in section 8.1 : ? asymmetric final stage in doherty configuration ? asymmetric driver for high power doherty amplifier blm7g1822s-40ab; blm7g1822s-40abg ldmos 2-stage power mmic rev. 1 ? 10 july 2015 product data sheet table 1. performance typical rf performance at t case = 25 ? c; i dq1 = 20 ma; i dq2 = 76 ma for carrier section: i dq1 = 40 ma and i dq2 = 120 ma for peaking section. test signal: 3gpp test model 1; single carri er w-cdma; 64 dpch; par = 9.9 db at 0.01% probability on ccdf; per section in a class-ab production circuit. test signal f v ds p l(av) g p ? d acpr 5m (mhz) (v) (w) (db) (%) (dbc) single carrier w-cdma carrier section 2167.5 28 2 31.5 25.5 ? 37 peaking section 2167.5 28 4 31.5 26.5 ? 38
blm7g1822s-40ab_s-40abg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 1 ? 10 july 2015 2 of 19 nxp semiconductors blm7g1822s-40ab(g) ldmos 2-stage power mmic 2. pinning information 2.1 pinning 2.2 pin description transparent top view the exposed backside of the package is the ground terminal of the device. fig 1. pin configuration ddd 9 '6$ 9 '6% 9 *6$ 9 *6% 9 *6$ 5)b287b$9 '6$ 5)b287b%9 '6% 9 *6% 5)b,1b$ 5)b,1b% qf qf qf qf qf qf slqlqgh[ table 2. pin description symbol pin description v ds(a1) 1 drain-source voltage of carrier section, driver stage (a1) v gs(a2) 2 gate-source voltage of carrier section, final stage (a2) v gs(a1) 3 gate-source voltage of carrier section, driver stage (a1) rf_in_a 4 rf input carrier section (a) n.c. 5 not connected n.c. 6 not connected n.c. 7 not connected n.c. 8 not connected n.c. 9 not connected n.c. 10 not connected rf_in_b 11 rf input peaking section (b) v gs(b1) 12 gate-source voltage of peaki ng section, driver stage (b1) v gs(b2) 13 gate-source voltage of peaking section, final stage (b2) v ds(b1) 14 drain-source voltage of peaking section, driver stage (b1)
blm7g1822s-40ab_s-40abg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 1 ? 10 july 2015 3 of 19 nxp semiconductors blm7g1822s-40ab(g) ldmos 2-stage power mmic 3. ordering information 4. block diagram 5. limiting values rf_out_b/v ds(b2) 15 rf output peaking section (b) / drain-source voltage of peaking section, final stage (b2) rf_out_a/v ds(a2) 16 rf output carrier section (a) / drain- source voltage of carrier section, final stage (a2) gnd flange rf ground table 2. pin description ?continued symbol pin description table 3. ordering information type number package name description version blm7g1822s-40ab hsop16f plastic, heatsink smal l outline package; 16 leads (flat) sot1211-2 blm7g1822s-40abg hsop16 plastic, heatsink small outline package; 16 leads sot1212-2 fig 2. block diagram ddd 9 '6$ 9 '6% 9 *6$ 5)b287b$9 '6$ 5)b287b%9 '6% 9 *6% 5)b,1b$ 5)b,1b% 7(03(5$785( &203(16$7('%,$6 9 *6% 9 *6$ 7(03(5$785( &203(16$7('%,$6 fduulhu shdnlqj table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v ds drain-source voltage - 65 v v gs gate-source voltage ? 0.5 +13 v
blm7g1822s-40ab_s-40abg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 1 ? 10 july 2015 4 of 19 nxp semiconductors blm7g1822s-40ab(g) ldmos 2-stage power mmic [1] continuous use at maximum temperature will affect the reliability. for details refer to the online mtf calculator. 6. thermal characteristics [1] when operated with a cw signal. 7. characteristics t stg storage temperature ? 65 +150 ?c t j junction temperature [1] -225 ?c t case case temperature - 150 ?c table 4. limiting values ?continued in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit table 5. thermal characteristics symbol parameter conditions value unit carrier section r th(j-c) thermal resistance from junction to case final stage; t case =90 ? c; p l = 1.78 w [1] 3.8 k/w driver stage; t case =90 ? c; p l = 1.78 w [1] 12.4 k/w peaking section r th(j-c) thermal resistance from junction to case final stage; t case =90 ? c; p l = 1.26 w [1] 2.4 k/w driver stage; t case =90 ? c; p l = 1.26 w [1] 7.6 k/w table 6. dc characteristics t case = 25 ? c; per section unless otherwise specified. symbol parameter conditions min typ max unit carrier section final stage v (br)dss drain-source breakdown voltage v gs =0v; i d = 150.8 ? a65--v v gsq gate-source quiescent voltage v ds =28 v; i d = 76 ma 1.6 2.1 2.6 v v ds =28 v; i d = 76 ma [1] 1.6 2.65 3.5 v ? i dq / ? t quiescent drain current variation with temperature ? 40 ?c ? t case ? +85 ? c [1] - ? 1- % i dss drain leakage current v gs =0v; v ds =28v - - 1.4 ? a i dsx drain cut-off current v gs = 5.65 v; v ds =10 v - 2.8 - a i gss gate leakage current v gs =1.0v; v ds =0v - - 140 na driver stage v (br)dss drain-source breakdown voltage v gs =0v; i d = 30.16 ? a65--v v gsq gate-source quiescent voltage v ds =28 v; i d = 20 ma 1.6 2.15 2.6 v v ds =28 v; i d = 20 ma [2] 1.6 2.7 3.5 v ? i dq / ? t quiescent drain current variation with temperature ? 40 ?c ? t case ? +85 ? c [2] - ? 1- % i dss drain leakage current v gs =0v; v ds =28v - - 1.4 ? a i dsx drain cut-off current v gs = 5.65 v; v ds = 10 v - 0.55 - a i gss gate leakage current v gs =1.0v; v ds =0v - - 140 na
blm7g1822s-40ab_s-40abg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 1 ? 10 july 2015 5 of 19 nxp semiconductors blm7g1822s-40ab(g) ldmos 2-stage power mmic [1] in production circuit with 1105.6 ? gate feed resistor. [2] in production circuit with 765 ? gate feed resistor. [3] in production circuit with 825.6 ? gate feed resistor. [4] in production circuit with 850 ? gate feed resistor. peaking section final stage v (br)dss drain-source breakdown voltage v gs =0v; i d = 302 ? a 65--v v gsq gate-source quiescent voltage v ds =28 v; i d = 120 ma 1.6 2.1 2.6 v v ds =28 v; i d = 120 ma [3] 1.6 2.65 3.5 v ? i dq / ? t quiescent drain current variation with temperature ? 40 ?c ? t case ? +85 ? c [3] - ? 1- % i dss drain leakage current v gs =0v; v ds =28v - - 1.4 ? a i dsx drain cut-off current v gs = 5.65 v; v ds =10 v - 5.4 - a i gss gate leakage current v gs =1.0v; v ds =0v - - 140 na driver stage v (br)dss drain-source breakdown voltage v gs =0v; i d = 58 ? a 65--v v gsq gate-source quiescent voltage v ds =28 v; i d = 40 ma 1.6 2.15 2.6 v v ds =28 v; i d = 40 ma [4] 1.6 2.7 3.5 v ? i dq / ? t quiescent drain current variation with temperature ? 40 ?c ? t case ? +85 ? c [4] - ? 1- % i dss drain leakage current v gs =0v; v ds =28v - - 1.4 ? a i dsx drain cut-off current v gs = 5.65 v; v ds = 10 v - 1.04 - a i gss gate leakage current v gs =1.0v; v ds =0v - - 140 na table 6. dc characteristics ?continued t case = 25 ? c; per section unless otherwise specified. symbol parameter conditions min typ max unit table 7. rf characteristics typical rf performance at t case = 25 ? c; v ds = 28 v; i dq1 = 20 ma (carrier section, driver stage); i dq2 = 76 ma (carrier section, final stage); p l(av) = 2 w (carrier section); i dq1 = 40 ma (peaking section, driver stage); i dq2 = 120 ma (peaking section, final stage); p l(av) = 4 w (peaking section) unless otherwise specified, measured in an nxp straight lead production circuit. symbol parameter conditions min typ max unit carrier section test signal: single carrier w-cdma [1] g p power gain f = 1807.5 mhz - 31.8 - db f = 2167.5 mhz 30 31.5 33 db ? d drain efficiency f = 1807.5 mhz - 18 - % f = 2167.5 mhz 21 25.5 - % rl in input return loss f = 2167.5 mhz - ? 15 ? 10 db acpr 5m adjacent channel power ratio (5 mhz) f = 1807.5 mhz - ? 39 - dbc f = 2167.5 mhz - ? 37 ? 33 dbc par o output peak-to-average ratio f = 1807.5 mhz - 8.4 - db f = 2167.5 mhz 6.4 7.7 - db
blm7g1822s-40ab_s-40abg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 1 ? 10 july 2015 6 of 19 nxp semiconductors blm7g1822s-40ab(g) ldmos 2-stage power mmic [1] 3gpp test model 1; 64 dpch; par = 9.9 db at 0.01% probability on ccdf. [2] f = 2170 mhz. 8. application information [1] for carrier and peaking sections (s-p arameters measured with load-pull jig). peaking section test signal: single carrier w-cdma [1] g p power gain f = 1807.5 mhz - 31.3 - db f = 2167.5 mhz 30 31.5 33 db ? d drain efficiency f = 1807.5 mhz - 25.5 - % f = 2167.5 mhz 22 26.5 - % rl in input return loss f = 2167.5 mhz - ? 20 ? 10 db acpr 5m adjacent channel power ratio (5 mhz) f = 1807.5 mhz - ? 41 - dbc f = 2167.5 mhz - ? 38 ? 34 dbc par o output peak-to-average ratio f = 1807.5 mhz - 8.2 - db f = 2167.5 mhz 6.5 7.9 - db test signal: cw [2] ?? s21 phase response difference no rmalized; between sections ? 10 - +10 deg ?? s 21 ? 2 insertion power gain difference normalized; between sections ? 0.5 - +0.5 db table 7. rf characteristics ?continued typical rf performance at t case = 25 ? c; v ds = 28 v; i dq1 = 20 ma (carrier section, driver stage); i dq2 = 76 ma (carrier section, final stage); p l(av) = 2 w (carrier section); i dq1 = 40 ma (peaking section, driver stage); i dq2 = 120 ma (peaking section, final stage); p l(av) = 4 w (peaking section) unless otherwise specified, measured in an nxp straight lead production circuit. symbol parameter conditions min typ max unit table 8. typical performance t case =25 ? c; v ds =28v; i dq1 =i dq2 = 100 ma (carrier section, driver and final stages); v gs1 = 2.55 v (peaking section, driver stage); v gs2 = 1.47 v (peaking section, final stage); test signal: 1-c w-cdma; tm1; 64 dpch; par 9.9db at 0.01% probability ccdf; in an nxp, f = 2110 mhz to 2170 mhz, doherty application circuit (see figure 3 and figure 4 ). symbol parameter conditions min typ max unit p l(3db) output power at 3 db gain compression f = 2140 mhz - 46.6 - w ? d drain efficiency 8 db obo (p l = 38.6 dbm); f = 2140 mhz - 36.5 - % g p power gain p l(av) = 7.25 w; f = 2140 mhz - 26.1 - db b video video bandwidth p l(av) = 7.25 w; f = 2140 mhz; 2-tone cw - 145 - mhz g flat gain flatness p l(av) =7.25w - 0.2 - db ? g/ ? t gain variation with temperature f = 2140 mhz [1] -0.03- db/ ?c k rollett stability factor t case = ? 40 ? c; f = 0.1 ghz to 3 ghz [1] - ? 1-
blm7g1822s-40ab_s-40abg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 1 ? 10 july 2015 7 of 19 nxp semiconductors blm7g1822s-40ab(g) ldmos 2-stage power mmic printed-circuit board (pcb): rogers 4350; thickness = 0.508 mm. fig 3. component layout for doherty application circuit s) s) s) ?) ?) ?) ?) ?) ?) ?) ?) ?) n n n n n /0 /0 g% g% s) s) s) ?) pp pp n pp pp ddd
blm7g1822s-40ab_s-40abg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 1 ? 10 july 2015 8 of 19 nxp semiconductors blm7g1822s-40ab(g) ldmos 2-stage power mmic 8.1 possible circuit topologies fig 4. electrical schematic ddd &$55,(5 3($.,1* %/0*6$% n n n n g% g% n /0 /0 ?) ?) ?) ?) ?) s) s) s) s) s) s) ?) ?) ?) ?) ?) 5)lq 5)rxw 9 *6 9 '6 9 '6 9 '6 9 '6 9 *6 fig 5. dual section ddd ,q $ g%-? g%-? ,q% 2xw$ 2xw%
blm7g1822s-40ab_s-40abg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 1 ? 10 july 2015 9 of 19 nxp semiconductors blm7g1822s-40ab(g) ldmos 2-stage power mmic 8.2 ruggedness in class-ab operation the blm7g1822s-40ab and blm7g1822s-40abg are capable of withstanding a load mismatch corresponding to vswr = 10 : 1 through all phases under the following conditions: v ds =32v; i dq1 = 20 ma and i dq2 = 75 ma for carrier section; i dq1 =40ma and i dq2 = 120 ma for peaking section; p i is corresponding to p l(3db) under z s = 50 ? load; f = 2140 mhz. fig 6. doherty ddd g%-? g%-? &rpelqhu 2xw 6solwwhu ,q
blm7g1822s-40ab_s-40abg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 1 ? 10 july 2015 10 of 19 nxp semiconductors blm7g1822s-40ab(g) ldmos 2-stage power mmic 8.3 impedance information table 9. typical impedance tuned for maximum output power measured load-pull data at 3 db gain compression point; test signal: pulsed cw; t case = 25 ? c; v ds = 28 v; i dq1 = 20 ma (carrier section, driver stage); i dq2 = 65 ma (carrier section, final stage); i dq1 = 40 ma (peaking section, driver stage); i dq2 = 130 ma (carrier section, final stage); t p =100 ? s; ? =10%; z s =50 ? . typical values unless otherwise specified. tuned for maximum output power tuned for maximum efficiency f z l g p(max) p l ? add am-pm z l g p(max) p l ? add am-pm (mhz) (? ) (db) (w) (%) (deg) (? ) (db) (w) (%) (deg) carrier section blm7g1822s-40ab 1700 15.3 ? j14.5 33.2 42.7 50.6 8.3 28.5 ? j20.2 34.6 41.6 56.5 9.2 1800 16.3 ? j11.7 32.9 42.7 50.8 6.3 31.3 ? j8.60 34.1 41.6 57.1 7.0 1900 16.1 ? j9.70 32.1 42.8 50.8 6.1 26.5 ? j0.01 33.3 41.7 57.3 6.9 2000 15.5 ? j8.10 31.5 42.8 50.1 6.1 21.0 + j2.20 32.6 42.0 56.4 7.3 2100 14.4 ? j6.90 31.5 42.9 50.0 6.9 15.6 + j2.00 32.9 42.1 55.8 8.6 2200 13.7 ? j6.60 31.7 42.7 49.8 8.5 12.3 + j1.20 33.0 41.6 54.3 9.6 2300 12.8 ? j6.80 31.4 42.5 49.1 10.6 10. 0 + j0.10 32.5 41.3 53.6 10.3 blm7g1822s-40abg 1700 15.8 ? j16.1 33.5 42.5 52.9 9.2 28.9 ? j21.8 35.1 41.6 57.9 11.1 1800 16.5 ? j13.8 32.9 42.5 51.2 7.7 30.6 ? j11.6 34.3 41.6 56.8 8.4 1900 16.7 ? j12.4 32.2 42.5 50.2 7.2 27.9 ? j4.64 33.5 41.7 55.9 7.8 2000 16.3 ? j9.74 31.7 42.5 51.2 7.3 20.4 + j0.45 32.7 41.7 55.6 9.0 2100 15.6 ? j8.61 31.5 42.6 52.0 9.5 15.9 + j0.68 32.6 41.7 56.4 11.8 2200 14.6 ? j8.87 31.3 42.5 49.7 10.3 12.7 ? j0.44 32.4 41.6 53.8 12.1 2300 13.4 ? j9.32 30.5 42.4 48.2 12.8 10.7 ? j1.98 31.7 41.6 53.7 13.2 peaking section blm7g1822s-40ab 1700 7.02 ? j10.1 33.4 45.4 51.2 1.0 13.6 ? j11.6 34.7 44.1 56.4 3.9 1800 7.10 ? j9.70 33.3 45.5 50.5 0.9 13.4 ? j7.20 34.4 44.3 57.2 2.9 1900 6.90 ? j10.0 32.6 45.6 48.8 ? 0.1 11.6 ? j5.20 33.6 44.4 56.7 2.2 2000 6.68 ? j10.2 32.6 45.6 49.4 ? 0.5 9.30 ? j4.80 33.5 44.5 56.1 2.1 2100 6.52 ? j10.2 33.3 45.6 49.3 4.1 7.20 ? j5.40 33.9 44.5 54.9 6.4 2200 6.39 ? j10.4 33.1 45.4 49.5 7.5 6.20 ? j6.30 33.8 44.5 54.6 8.5 2300 5.83 ? j10.5 31.5 45.1 50.2 11.2 5.50 ? j7.50 32.4 44.4 54.5 12.2 blm7g1822s-40abg 1 700 6.43 ? j11.5 32.5 45.4 53.9 1.9 13.8 ? j13.4 33.9 44.0 61.0 3.2 1800 6.54 ? j11.8 32.3 45.4 52.5 1.2 14.5 ? j10.0 33.7 44.2 59.4 2.8 1900 6.59 ? j12.2 32.3 45.5 51.8 ? 6 13.0 ? j8.07 33.5 44.3 58.9 2.4 2000 6.49 ? j12.1 32.5 45.5 51.3 ? 1.7 9.21 ? j7.30 33.6 44.5 57.2 1.2 2100 6.48 ? j12.1 32.7 45.6 50.7 3.4 7.36 ? j7.91 33.6 44.6 57.1 2.4 2200 6.12 ? j12.4 32.6 45.3 51.2 8.2 6.21 ? j8.66 33.5 44.4 56.8 7.5 2300 5.78 ? j12.4 31.8 45.0 52.0 10.9 5.34 ? j9.17 32.5 44.2 56.7 11.5
blm7g1822s-40ab_s-40abg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 1 ? 10 july 2015 11 of 19 nxp semiconductors blm7g1822s-40ab(g) ldmos 2-stage power mmic 8.4 graphs t case = 25 ? c; v ds =28v; p l =6.3w; i dq1 =i dq2 = 100 ma (carrier section, driver and final stages); v gs1 = 2.55 v (peaking section, driver stage); v gs2 = 1.47 v (peaking section, final stage). test signal: cw (1) magnitude of g p (2) magnitude of rl in t case = 25 ? c; v ds =28v; p l =6.3w; i dq1 =i dq2 = 100 ma (carrier section, driver and final stages); v gs1 = 2.55 v (peaking section, driver stage); v gs2 = 1.47 v (peaking section, final stage). test signal: cw (1) magnitude of g p (2) magnitude of rl in fig 7. wideband power gain and input return loss as function of frequency; typical values fig 8. in-band power gain and input return loss as function of frequency; typical values ddd i0+] * s * s g% g% g% 5/ 5/ lq lq 5/ lq g% g% g% ddd i0+] * s * s g% g% g% 5/ 5/ lq lq 5/ lq g% g% g%
blm7g1822s-40ab_s-40abg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 1 ? 10 july 2015 12 of 19 nxp semiconductors blm7g1822s-40ab(g) ldmos 2-stage power mmic t case = 25 ? c; v ds =28v; i dq1 =i dq2 = 100 ma (carrier section, driver and final stages); v gs1 = 2.55 v (peaking section, driver stage); v gs2 = 1.47 v (peaking section, final stage). test signal: cw (1) f = 2110 mhz (2) f = 2140 mhz (3) f = 2170 mhz t case = 25 ? c; v ds =28v; i dq1 =i dq2 = 100 ma (carrier section, driver and final stages); v gs1 = 2.55 v (peaking section, driver stage); v gs2 = 1.47 v (peaking section, final stage). test signal: cw (1) f = 2110 mhz (2) f = 2140 mhz (3) f = 2170 mhz fig 9. power gain as a function of output power; typical values fig 10. normalized phase response as a function of output power; typical values t case = 25 ? c; v ds =28v; i dq1 =i dq2 = 100 ma (carrier section, driver and final stages); v gs1 = 2.55 v (peaking section, driver stage); v gs2 = 1.47 v (peaking section, final stage). test signal: 2-tone cw; f c = 2140 mhz. (1) imd low (2) imd high fig 11. intermodulation distortion as a function of tone spacing; typical values ddd 3 / g%p * s * s g% g% g% ddd 3 / g%p 3 v v 3 3 vqrup vqrup 3 v 3 vqrup ghj ghj ghj ddd wrqhvsdflqj0+] ,0' ,0' ,0' g%f g%f g%f ,0' ,0' ,0' ,0' ,0' ,0' ,0' ,0' ,0'
blm7g1822s-40ab_s-40abg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 1 ? 10 july 2015 13 of 19 nxp semiconductors blm7g1822s-40ab(g) ldmos 2-stage power mmic t case = 25 ? c; v ds =28v; i dq1 =i dq2 = 100 ma (carrier section, driver and final stages); v gs1 = 2.55 v (peaking section, driver stage); v gs2 = 1.47 v (peaking section, final stage). test signal: 1-carrier w-cdma; test model 1; 64 dpch; par 9.9 db at 0.01% probability ccdf; f = 2140 mhz. t case = 25 ? c; v ds =28v; i dq1 =i dq2 = 100 ma (carrier section, driver and final stages); v gs1 = 2.55 v (peaking section, driver stage); v gs2 = 1.47 v (peaking section, final stage). test signal: 1-carrier w-cdma; test model 1; 64 dpch; par 9.9 db at 0.01% probability ccdf; f = 2140 mhz. fig 12. power gain and drain efficiency as function of output power; typical values fig 13. adjacent channel power ratio as a function of output power; typical values t case = 25 ? c; v ds =28v; i dq1 =i dq2 = 100 ma (carrier section, driver and final stages); v gs1 = 2.55 v (peaking section, driver stage); v gs2 = 1.47 v (peaking section, final stage). test signal: 1-carrier w-cdma; test model 1; 64 dpch; par 9.9 db at 0.01% probability ccdf; f = 2140 mhz. fig 14. output peak-to-average ratio and peak output power as function of output power; typical values ddd 3 / g%p * s * s g% g% g% ' ' * s * s ' ' ddd 3 / g%p $&35 $&35 $&35 g%f g%f g%f $&35 $&35 0 0 $&35 0 $&35 $&35 0 0 $&35 0 ddd 3 / g%p 3$5 3$5 2 3$5 2 g% g% g% 3 /0 /0 3 /0 g% g% g% 3$5 3$5 2 3$5 2 3 /0 /0 3 /0
blm7g1822s-40ab_s-40abg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 1 ? 10 july 2015 14 of 19 nxp semiconductors blm7g1822s-40ab(g) ldmos 2-stage power mmic 9. package outline fig 15. package outline sot1211-2 (hsop16f) 5hihuhqfhv 2xwolqh yhuvlrq (xurshdq surmhfwlrq ,vvxhgdwh ,(& -('(& -(,7$ 627 vrwbsr 8qlw pp pd[ qrp plq $ +623)sodvwlfkhdwvlqnvpdoorxwolqhsdfndjhohdgviodw 627 $ $ e e f' ' ) ' ' ( ( ( ( h hh h h h h \ + ( 4 yz vfdoh ghwdlo; h ' ' h p p ' % \ % z ( ( slq lqgh[ e [ % z e[ $ $ 4 $ $ ( f + ( ' ( y$ ; 'lphqvlrqvppduhwkhruljlqdoglphqvlrqv h [ h [ h [ [ h [ h [0(7$/ 3527586,2166285&( )[ 1rwh 3dfndjherg\glphqvlrqv3'dqg3(grqrwlqfoxghprogdqgph wdosurwuxvlrqv$oorzdeohsurwuxvlrqlvppshuvlgh /hdgzlgwkglphqvlrqv3edqg3 e grqrwlqfoxghgdpedusurwuxvlrqv$oorzdeohgdpedusurwuxvlrqlvpplqwrwdoshuohdg
blm7g1822s-40ab_s-40abg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 1 ? 10 july 2015 15 of 19 nxp semiconductors blm7g1822s-40ab(g) ldmos 2-stage power mmic fig 16. package outline sot1212-2 (hsop16) ' 5hihuhqfhv 2xwolqh yhuvlrq (xurshdq surmhfwlrq ,vvxhgdwh ,(& -('(& -(,7$ 627 vrwbsr +623sodvwlfkhdwvlqnvpdoorxwolqhsdfndjhohdgv 627 ghwdlo; h ' ( f + ( ( ( [0(7$/ 3527586,2166285&( ' ' \ % + $ y$ ; z% e [ z% e [ $ 4 $ $ $ $ slqlqgh[ h h [ h [ [ / s h ( h [ h [ ? 8qlw pp pd[ qrp plq $ 'lphqvlrqvppduhwkhruljlqdoglphqvlrqv 1rwh 3dfndjherg\glphqvlrqv3'

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blm7g1822s-40ab_s-40abg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 1 ? 10 july 2015 16 of 19 nxp semiconductors blm7g1822s-40ab(g) ldmos 2-stage power mmic 10. handling information 11. abbreviations 12. revision history caution this device is sensitive to electrostatic di scharge (esd). observe precautions for handling electrostatic sensitive devices. such precautions are described in the ansi/esd s20.20 , iec/st 61340-5 , jesd625-a or equivalent standards. table 10. abbreviations acronym description am amplitude modulation 3gpp 3rd generation partnership project ccdf complementary cumulative distribution function cw continuous wave dpch dedicated physical channel esd electrostatic discharge gen7 seventh generation ldmos laterally diffused metal oxide semiconductor mmic monolithic microwave integrated circuit mtf median time to failure obo output back off par peak-to-average ratio pm phase modulation vswr voltage standing-wave ratio w-cdma wideband code division multiple access table 11. revision history document id release date data sheet status change notice supersedes blm7g1822s-40ab_s-40abg v.1 20150710 product data sheet - -
blm7g1822s-40ab_s-40abg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 1 ? 10 july 2015 17 of 19 nxp semiconductors blm7g1822s-40ab(g) ldmos 2-stage power mmic 13. legal information 13.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 13.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 13.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
blm7g1822s-40ab_s-40abg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. product data sheet rev. 1 ? 10 july 2015 18 of 19 nxp semiconductors blm7g1822s-40ab(g) ldmos 2-stage power mmic export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 13.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 14. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors blm7g1822s-40ab(g) ldmos 2-stage power mmic ? nxp semiconductors n.v. 2015. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 10 july 2015 document identifier: blm7g1822s-40ab_s-40abg please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 15. contents 1 product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 general description . . . . . . . . . . . . . . . . . . . . . 1 1.2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 1.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 pinning information . . . . . . . . . . . . . . . . . . . . . . 2 2.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 thermal characteristics . . . . . . . . . . . . . . . . . . 4 7 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 application information. . . . . . . . . . . . . . . . . . . 6 8.1 possible circuit topologies . . . . . . . . . . . . . . . . 8 8.2 ruggedness in class-ab operation . . . . . . . . . 9 8.3 impedance information . . . . . . . . . . . . . . . . . . 10 8.4 graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9 package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 10 handling information. . . . . . . . . . . . . . . . . . . . 16 11 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 13 legal information. . . . . . . . . . . . . . . . . . . . . . . 17 13.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 13.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 14 contact information. . . . . . . . . . . . . . . . . . . . . 18 15 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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